1. Field of the Invention
The present invention relates to a method for testing a memory cell by controlling a sense amplifier of a memory device, and more particularly to a test method capable of previously detecting a column fail of a memory device by adjusting a timing of driving voltage applied to a sense amplifier when a wafer level test is carried out.
2. Description of the Prior Art
As is generally known in the art, semiconductor wafers are subject to at least two test processes (that is, a wafer level test and a package level test) before the semiconductor wafers have been fabricated as semiconductor articles. Such test processes for the semiconductor wafers are inevitably necessary in order to achieve semiconductor articles having no defects.
The test processes are carried out with respect to all internal parts of a semiconductor device, such as a memory device. Therefore, such test processes are also carried out with respect to a memory cell of the memory device storing data, which relates to the present invention.
Conventionally, when a defect of a memory cell is found during a wafer level test, a repair fuse of a word line or a bit line connected to a detected cell is cut so as to replace the defected cell with a redundancy cell.
In contrast, if the defect of the memory cell is found during a package level test, a method utilizing an anti-fuse is used. However, in order to realize the above method utilizing the anti-fuse, an additional circuit is necessary, so a size of a memory chip is enlarged and a yield rate is decreased.